1. Field of the Invention
The present invention relates to amplifiers and more particularly to amplifiers having improved performance and reliability over a wide range of supply voltages.
2. Description of Related Art
Persons of ordinary skill in the art will understand terms used in this application. For example, terms like MOS (metal-oxide semiconductor) transistor, “gate,” “source,” “drain,” “channel length,” “threshold voltage,” “saturation region,” and “triode region,” as used in connection with a MOS transistor, and basic concepts for electronic circuits, such as: “voltage,” “current,” “trans-conductance,” “output resistance,” “biasing,” “self-biasing,” “single-ended,” “differential,” “pseudo-differential,” “common-mode,” “common-source,” “common-gate,” “cascade,” and “cascode” will be readily understood. Terms like these are readily apparent from prior art documents like text books, e.g. “Design of Analog CMOS Integrated Circuits” by Behzad Razavi, McGraw-Hill (ISBN 0-07-118839-8).
As depicted in FIG. 1, a prior art differential amplifier 100 comprises: a current source 110 comprising NMOS (n-channel metal-oxide semiconductor transistor) 111 and 112 for outputting biasing currents I1 and I2 in accordance with a biasing voltage VB; a differential pair 120 comprising NMOS 121 and 122 for receiving biasing currents I1 and I2, so as to amplify a differential input signal VI (which comprises two ends VI+ and VI) into a differential output signal VO (which comprises two ends VO+ and VO); and a load comprising resistors 131 and 132 for providing termination for the differential output signal VO. Throughout this disclosure, VDD denotes a power supply voltage. Differential amplifier 100 is well known in prior art and thus not described in detail here. Barring a device mismatch due to finite tolerance in a manufacturing process, it is assumed that the differential amplifier 100 is symmetrical; that is, NMOS 111 and 112 are substantially the same, NMOS 121 and 122 are substantially the same, and resistors 131 and 132 are substantially the same. When using an advanced CMOS (complementary metal oxide semiconductor) process to manufacture differential amplifier 100, there is an issue that needs to be addressed. The supply voltage VDD is low, for instance 1V for a typical 28 nm CMOS process. Also, it is highly desirable, if not mandatory, that the differential input signal VI and the differential output signal VO are of the same common-mode value (i.e., (VI++VI)/2=(VO++VO)/2), so that a plurality of differential amplifiers of the same circuits can be easily cascaded. To fulfill effective amplification, NMOS transistors 121 and 122 of the differential pair 120 must be biased in the saturation region. To be biased in the saturation region, the static gate-to-source voltage (of NMOS transistors 121 and 122) must be greater than the threshold voltage (of NMOS transistors 121 and 122); therefore, the static voltage drop, which is the drain-to-source voltage (of NMOS transistors 121 and 122), also must be greater than the threshold voltage (of NMOS transistors 121 and 122). Also, for the current source 110 to have high output resistance that is highly desirable, NMOS transistors 111 and 112 also must operate in the saturation region where the voltage drop (between drain and source) cannot be too small, or else NMOS 111 and 112 might enter the triode region where output resistance cannot be very high.
On the other hand, the available swing for the differential output signal VO is determined by the voltage drop on the load devices (i.e., resistors 131 and 132). The total sum of the voltage drops across the load 130, differential pair 120, and the current source 110, however, is equal to the supply voltage VDD; if the voltage drop on the differential pair 120 is increased, the voltage drop allowed for the load 130 must be reduced, assuming the voltage drop for the current source 110 cannot be squeezed or else NMOS 111 and 112 might enter the triode region. For a typical 28 nm CMOS process, the threshold voltage of a MOS transistor depends on the channel length of the MOS transistor; a shorter channel MOS transistor allows a higher trans-conductance and thus a higher operation speed but unfortunately also has a higher threshold voltage. Due to the higher threshold voltage, the voltage drop across the differential pair 120 is greater, leaving less available swing for the differential output signal VO. Therefore, there is a trade-off between speed and available swing. Also, in an application circuit, the supply voltage VDD is subject to variation.
While a differential amplifier may function sufficiently well under a normal supply voltage, the performance may quickly degrade and even become dysfunctional in an over-stressed condition when the supply voltage drops to a certain low level. To ensure that the differential amplifier 100 remains functional under the lowest supply voltage that can be anticipated in an over-stressed condition, circuit designers are forced to use a longer channel length at the cost of reduced speed and performance at normal supply voltage.